H8SXSLASH1663 datasheet(537/1158 Pages) RENESAS

537 / 1158 page

Section 9 I/O Ports

Rev.1.00 Jun. 07, 2006 Page 485 of 1102

REJ09B0294-0100

Bit

Bit Name

Initial

Value

R/W

Description

CS4SA*

CS4SB*

R/W

CS4 Output Pin Select

Selects the output pin for

CS4 when CS4 output is

enabled (CS4E = 1)

00: Specifies pin PB1 as

CS4-A output

01: Specifies pin PB0 as

CS4-B output

10: Setting prohibited

11: Setting prohibited

Note:

If multiple

CS outputs are specified to a single pin according to the CSn output pin

select bits (n = 4 to 7), multiple

CS signals are output from the pin. For details, see

section 6.5.3, Chip Select Signals.

9.3.3

Port Function Control Register 2 (PFCR2)

PFCR2 selects the

CS output pin, enables/disables bus control I/O, and selects the bus control I/O

pins.

Bit

Bit Name

Initial Value

R/W



CS2S

R/W

BSS

R/W

BSE

R/W

RDWRS

R/W

RDWRE

R/W

ASOE

R/W



Bit

Bit Name

Initial

Value

R/W

Description



Reserved

This bit is always read as 0. The write value should

always be 0.

CS2S*

R/W

CS2 Output Pin Select

Selects the output pin for

CS2 when CS2 output is

enabled (CS2E = 1)

0: Specifies pin PB2 as

CS2-A output pin

1: Specifies pin PB1 as

CS2-B output pin

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