H8SXSLASH1663 datasheet(554/1158 Pages) RENESAS

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Section 10 16-Bit Timer Pulse Unit (TPU)

Rev.1.00 Jun. 07, 2006 Page 502 of 1102

REJ09B0294-0100

10.3

The TPU has the following registers in each channel.

• Channel 0

 Timer control register_0 (TCR_0)

 Timer mode register_0 (TMDR_0)

 Timer I/O control register H_0 (TIORH_0)

 Timer I/O control register L_0 (TIORL_0)

 Timer interrupt enable register_0 (TIER_0)

 Timer status register_0 (TSR_0)

 Timer counter_0 (TCNT_0)

 Timer general register A_0 (TGRA_0)

 Timer general register B_0 (TGRB_0)

 Timer general register C_0 (TGRC_0)

 Timer general register D_0 (TGRD_0)

• Channel 1

 Timer control register_1 (TCR_1)

 Timer mode register_1 (TMDR_1)

 Timer I/O control register _1 (TIOR_1)

 Timer interrupt enable register_1 (TIER_1)

 Timer status register_1 (TSR_1)

 Timer counter_1 (TCNT_1)

 Timer general register A_1 (TGRA_1)

 Timer general register B_1 (TGRB_1)

• Channel 2

 Timer control register_2 (TCR_2)

 Timer mode register_2 (TMDR_2)

 Timer I/O control register_2 (TIOR_2)

 Timer interrupt enable register_2 (TIER_2)

 Timer status register_2 (TSR_2)

 Timer counter_2 (TCNT_2)

 Timer general register A_2 (TGRA_2)

 Timer general register B_2 (TGRB_2)

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