H8SXSLASH1663 datasheet(557/1158 Pages) RENESAS

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Section 10 16-Bit Timer Pulse Unit (TPU)

Rev.1.00 Jun. 07, 2006 Page 505 of 1102

REJ09B0294-0100

Table 10.3

CCLR2 to CCLR0 (Channels 0 and 3)

Channel

Bit 7

CCLR2

Bit 6

CCLR1

Bit 5

CCLR0

Description

TCNT clearing disabled

TCNT cleared by TGRA compare match/input

capture

TCNT cleared by TGRB compare match/input

capture

TCNT cleared by counter clearing for another

channel performing synchronous clearing/

synchronous operation*

TCNT clearing disabled

TCNT cleared by TGRC compare match/input

capture*

TCNT cleared by TGRD compare match/input

capture*

0, 3

TCNT cleared by counter clearing for another

channel performing synchronous clearing/

synchronous operation*

Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1.

2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the

buffer register setting has priority, and compare match/input capture does not occur.

Table 10.4

CCLR2 to CCLR0 (Channels 1, 2, 4, and 5)

Channel

Bit 7

Reserved*

Bit 6

CCLR1

Bit 5

CCLR0

Description

TCNT clearing disabled

TCNT cleared by TGRA compare match/input

capture

TCNT cleared by TGRB compare match/input

capture

1, 2, 4, 5

TCNT cleared by counter clearing for another

channel performing synchronous clearing/

synchronous operation*

Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1.

2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be

modified.

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