H8SXSLASH1663 datasheet(556/1158 Pages) RENESAS

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Section 10 16-Bit Timer Pulse Unit (TPU)

Rev.1.00 Jun. 07, 2006 Page 504 of 1102

REJ09B0294-0100

10.3.1

Timer Control Register (TCR)

TCR controls the TCNT operation for each channel. The TPU has a total of six TCR registers, one

for each channel. TCR register settings should be made only while TCNT operation is stopped.

CCLR2

R/W

CCLR1

R/W

CCLR0

R/W

CKEG1

R/W

CKEG0

R/W

TPSC2

R/W

TPSC1

R/W

TPSC0

R/W

Bit

Bit Name

Initial Value

R/W

Bit

Bit Name

Initial

Value

R/W

Description

CCLR2

CCLR1

CCLR0

R/W

Counter Clear 2 to 0

These bits select the TCNT counter clearing source. See

tables 10.3 and 10.4 for details.

CKEG1

CKEG0

R/W

Clock Edge 1 and 0

These bits select the input clock edge. For details, see

table 10.5. When the input clock is counted using both

edges, the input clock period is halved (e.g. P

φ/4 both

edges = P

φ/2 rising edge). If phase counting mode is

used on channels 1, 2, 4, and 5, this setting is ignored

and the phase counting mode setting has priority. Internal

clock edge selection is valid when the input clock is P

φ/4

or slower. This setting is ignored if the input clock is P

φ/1,

or when overflow/underflow of another channel is

selected.

TPSC2

TPSC1

TPSC0

R/W

Timer Prescaler 2 to 0

These bits select the TCNT counter clock. The clock

source can be selected independently for each channel.

See tables 10.6 to 10.11 for details. To select the external

clock as the clock source, the DDR bit and ICR bit for the

corresponding pin should be set to 0 and 1, respectively.

For details, see section 9, I/O Ports.

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