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H8SX/1663R Datenblatt(PDF) 361 Page - Renesas Technology Corp

Teilenummer H8SX/1663R
Bauteilbeschribung  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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Hersteller  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R Datenblatt(HTML) 361 Page - Renesas Technology Corp

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Section 9 Bus Controller (BSC)
Rev. 2.00 Sep. 24, 2008 Page 329 of 1468
REJ09B0412-0200
The time between the PALL or PRE command and the subsequent REF command can be changed
by wait cycle insertion. The number of wait cycles is selected from one to three cycles by bits
TPC1 and TPC0 in DRACCR. Set the bit according to the SDRAM to be used and the frequency
of this LSI so that the number of wait cycles can be optimal.
Figure 9.77 shows a timing example when the one wait cycles are inserted.
TR
p1
TR
p2
TR
r
TR
c1
TR
c2
CS
Precharge-sel
RAS
CAS
WE
CKE
PALL
REF
NOP
NOP
BS
RD/
WR
High
High
High
Address bus
SDRAM
φ
Figure 9.77 Auto-Refresh Timing (TPC1 = 0, TPC0 = 1)



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