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H8SX/1663R Datenblatt(PDF) 374 Page - Renesas Technology Corp

Teilenummer H8SX/1663R
Bauteilbeschribung  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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Hersteller  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R Datenblatt(HTML) 374 Page - Renesas Technology Corp

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Section 9 Bus Controller (BSC)
Rev. 2.00 Sep. 24, 2008 Page 342 of 1468
REJ09B0412-0200
(4)
When CKSPE = 1
When the SDRAM space is read, the read data settling cycle can be inserted for one cycle using
the clock suspend mode. To enter the clock suspend mode, set the OEE bit in DRAMCR to 1, and
connect the CKE pin.
Figure 9.88 shows an output timing example of the
DACK and EDACK signals when CKSPE = 1
with DDS = 1, EDDS = 1, DKC = 0 and EDKC = 0.
T
p
T
r
T
c1
T
cl
T
sp
T
c2
T
c1
T
cl
T
sp
T
c2
CS
Precharge-sel
RAS
CAS
WE
CKE
PALL ACTV READ
READ
NOP
NOP
DQMLU
DQMLL
D7 to D0
BS
DACK or EDACK
RD/
WR
D15 to D8
SDRAM
φ
Address bus
Row address
Column address 2
Column address 1
Row
address
Figure 9.88 Output Timing Example of
DACK and EDACK when CKSPE = 1
(Read, CAS Latency = 2)



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