H8SXSLASH1663R datasheet(375/1504 Pages) RENESAS

Teilenummer	H8SX/1663R

Bauteilbeschribung	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 343 of 1468

REJ09B0412-0200

(5)

When DKC = 1

With DKC = 1 or EDKC = 1, the

DACK and EDACK signals are asserted a half cycle earlier

compared to the case when DKC = 0 or EDKC = 0.

In fast-page access, the

DACK signal continues to be low. In this case, bus cycles can be

distinguished by the

BS output timing.

Figure 9.89 shows an output timing example of the

DACK and EDACK signals when DKC = 1 or

EDKC = 1, and DDS = 1 or EDDS = 1. Figure 9.90 shows an output timing example of the

DACK

and

EDACK signals when DKC = 1 or EDKC = 1, and DDS = 0 or EDDS = 0.

Address bus

Row address

Column address 2

Column address 1

SDRAM

Precharge-sel

RAS

CAS

CKE

PALL

ACTV

NOP

WRIT

DQMLU

DQMLL

D7 to D0

DACK or EDACK

RD/

D15 to D8

Row

address

High

Figure 9.89 Output Timing Example of

DACK and EDACK when DKC = 1 or EDKC = 1

and DDS = 1 or EDDS = 1 (Write)

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