H8SXSLASH1663R datasheet(376/1504 Pages) RENESAS

Teilenummer	H8SX/1663R

Bauteilbeschribung	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1504 Pages

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Hersteller	RENESAS [Renesas Technology Corp]

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Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 344 of 1468

REJ09B0412-0200

Address bus

Row address

Cloumn address

SDRAM

Precharge-sel

RAS

CAS

CKE

PALL

ACTV

WRIT

NOP

DQMLU

DQMLL

D7 to D0

RD/

D15 to D8

Row

address

High

DACK or EDACK

Figure 9.90 Output Timing Example of

DACK and EDACK when DKC = 1 or EDKC = 1

and DDS = 0 or EDDS = 0 (Write)

9.11.16

EXDMAC Cluster Transfer

Using an EXDMAC cluster transfer mode, data can be read from or written to consecutively. For

details, see section 11, EXDMA Controller (EXDMAC).

Figures 9.91 and 9.92 show a read/write timing using a cluster transfer.

For 1-cycle read or write, set the BE bit in DRAMCR to 1, clear the TRWL bit in SDCR to 0, and

set the CAS latency to 2. During a read cycle, the clock suspend mode cannot be used.

Do not change the bus controller register settings during a cluster transfer.

H8SX/1663R Datenblatt(PDF) 376 Page - Renesas Technology Corp