H8SXSLASH1663R datasheet(393/1504 Pages) RENESAS

Teilenummer	H8SX/1663R

Bauteilbeschribung	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 361 of 1468

REJ09B0412-0200

• When SCKCR is written to set the clock frequencies

If an external bus release request, external access, and a refresh request occur simultaneously, the

order of priority is as follows:

Refresh > EXDMAC > External bus release > External access by CPU, DTC, and

DMAC

9.13.2

Pin States in External Bus Released State

Table 9.32 shows pin states in the external bus released state.

Table 9.32

Pin States in Bus Released State

Pins

Pin State

A23 to A0

High impedance

D15 to D0

High impedance

CSn (n = 7 to 0)

High impedance

RD/

High impedance

LUCAS, LLCAS

High impedance

RAS

High impedance

CAS

High impedance

DQMLU, DQMLL

High impedance

CKE

High impedance

LUB, LLB

High impedance

LHWR, LLWR

High impedance

DACKn (n = 3 to 0)

High

EDACKn (n = 3 to 0)

High

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