H8SXSLASH1663R datasheet(395/1504 Pages) RENESAS

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Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 363 of 1468

REJ09B0412-0200

SDRAM

Address bus

RAS

CAS

Precharge-sel

NOP

PALL NOP

NOP

Hi-Z

[1]

[2]

[3]

[4]

[9]

[5]

[6]

[7]

[8]

Hi-Z

CS2

Hi-Z

CKE

BREQ

BACK

BREQO

Hi-Z

Data bus

DQMLU, DQMLL

External

access cycle

CPU cycle

External bus released state

[1] A low level of the

BREQ signal is sampled at the rising edge of the Bφ signal.

[2] The PALL command is issued.

[3] The bus control signals are driven high at the end of the external access cycle. It takes two cycles or

more after the low level of the

BREQ signal is sampled.

[4] The

BACK signal is driven low, releasing bus to the external bus master.

[5] The

BREQ signal state sampling is continued in the external bus released state.

[6] A high level of the

BREQ signal is sampled.

[7] The

BACK signal is driven high, ending external bus release cycle after one cycle.

[8] When the external space is accessed by an internal bus master or a refresh cycle is requested during external

bus released while the BREQOE bit is set to 1, the

BREQO signal goes low.

[9] Normally the

BREQO signal goes high at the rising edge of the BACK signal.

Figure 9.103 Bus Released State Transition Timing (SRAM Interface is Used)

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