H8SXSLASH1663R datasheet(404/1504 Pages) RENESAS

404 / 1504 page

Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 372 of 1468

REJ09B0412-0200

Also, since clock oscillation halts in software standby mode, if the

BREQ signal goes low in this

mode, indicating an external bus release request, the request cannot be answered until the chip has

recovered from the software standby mode.

Note that the

BACK and BREQO pins are both in the high-impedance state in software standby

mode.

(5)

External Bus Release Function and CBR-Refresh or Auto-Refresh Cycle

The CBR refresh or auto-refresh cycle cannot be performed while the external bus is released.

When a CBR-refresh or an auto-refresh cycle is requested, the BREQO signal can be output by

setting the BREQOE bit in BCR1 to 1.

(6)

BREQO Output Timing

When the BREQOE bit is set to 1 and the

BREQO signal is output, both the BREQO and BACK

signals may go low simultaneously.

This will occur if the next external access request occurs while internal bus arbitration is in

progress after the chip samples a low level of the

BREQ signal.

(7)

Refresh Settings

In single-chip activation mode, the setting of the RFSHE bit in REFCR should be made after

setting the EXPE bit in SYSCR to 1. For SYSCR, see section 3, MCU Operating Modes.

(8)

Refresh Timer Settings

The setting of bits RTCK2 to RTCK0 in REFCR should be made after RTCNT and RTCOR have

been set. When changing RTCNT and RTCOR, the counter operation should be halted. When

changing bits RTCK2 to RTCK0, external access and external bus release by the EXDMAC

should be prohibited. The write data buffer function should be used after the write data buffer

function is disabled and the external space is read.

(9)

Switching Between Refresh Timer and Interval Timer

When changing the RFSHE bit in REFCR from 1 to 0, a refresh cycle may be inserted until the bit

change is reflected. After this, when using RTCNT as an interval timer, the compare match flag

(CMF) may be set to 1. Therefore, confirm the state before setting the CMIE bit to 1.

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