H8SXSLASH1663R datasheet(435/1504 Pages) RENESAS

435 / 1504 page

Section 10 DMA Controller (DMAC)

Rev. 2.00 Sep. 24, 2008 Page 403 of 1468

REJ09B0412-0200

Transfer

Address TA

Address BA

Address update setting is as follows:

Source address increment

Fixed destination address

Address TB

Figure 10.3 Operations in Dual Address Mode

(2)

Single Address Mode

In single address mode, data between an external device and an external memory is directly

transferred using the

DACK pin instead of DSAR or DDAR. A transfer at a time is performed in

one bus cycle. In this mode, the data bus width must be the same as the data access size. For

details on the data bus width, see section 9, Bus Controller (BSC).

The DMAC accesses an external device as the transfer source or destination by outputting the

strobe signal (

DACK) to the external device with DACK and accesses the other transfer target by

outputting the address. Accordingly, the DMA transfer is performed in one bus cycle. Figure 10.4

shows an example of a transfer between an external memory and an external device with the

DACK pin. In this example, the external device outputs data on the data bus and the data is written

to the external memory in the same bus cycle.

The transfer direction is decided by the DIRS bit in DACR which specifies an external device with

the

DACK pin as the transfer source or destination. When DIRS = 0, data is transferred from an

external memory (DSAR) to an external device with the

DACK pin. When DIRS = 1, data is

transferred from an external device with the

DACK pin to an external memory (DDAR). The

settings of registers which are not used as the transfer source or destination are ignored.

The

DACK signal output is enabled in single address mode by the DACKE bit in DMDR. The

DACK signal is low active.

The

TEND signal output is enabled or disabled by the TENDE bit in DMDR. The TEND signal is

output in one bus cycle. When an idle cycle is inserted before the bus cycle, the

TEND signal is

also output in the idle cycle.

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