H8SXSLASH1663R datasheet(534/1504 Pages) RENESAS

534 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 502 of 1468

REJ09B0412-0200

(5)

DTE Bit in EDMDR

The DTE bit in EDMDR is written to by the CPU to control enabling and disabling of data

transfer, but may be cleared to 0 automatically by the EXDMAC due to the EXDMA transfer

status.

Conditions for DTE bit clearing by the EXDMAC include the following:

• When the specified total transfer size is completely transferred

• A transfer size error interrupt is requested, and transfer ends

• A repeat size end interrupt is requested, and transfer ends

• When an extended repeat area overflow interrupt is requested, and transfer ends

• When an NMI interrupt is generated, and transfer halts

• When an address error is generated, and transfer halts

• A reset

• Hardware standby mode

• When 0 is written to the DTE bit, and transfer halts

Writes (except to the DTE bit) are prohibited to registers of a channel for which the DTE bit is set

to 1. When changing register settings after a 0-write to the DTE bit, it is necessary to confirm that

the DTE bit has been cleared to 0.

Figure 11.21 shows the procedure for changing register settings in an operating channel.

[1] Write 0 to the DTE bit in EDMDR

[2] Read DTE bit.

[3] Confirm that DTE bit = 0. If DTE bit = 1,

this indicates that EXDMA transfer is in progress.

[4] Write the required set values to the registers.

Read DTE bit

Write 0 to DTE bit

Change register settings

DTE bit = 0

[1]

[2]

[3]

[4]

Yes

Changing register settings

in operating channel

changes completed

Figure 11.21 Procedure for Changing Register Settings in Operating Channel

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