H8SXSLASH1663R datasheet(535/1504 Pages) RENESAS

535 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 503 of 1468

REJ09B0412-0200

(6)

ACT bit in EDMDR

The ACT bit in EDMDR indicates whether the EXDMAC is in standby or active state. When DTE

= 0 and DTE = 1 (transfer request wait status) are specified, the ACT bit is set to 0. In another case

(EXDMAC in the active state), the ACT bit is set to 1. The ACT bit is held to 1 during EXDMA

transfer even if 0 is written to the DTE bit to halt transfer.

In block transfer mode, a block-size transfer is not halted even if 0 is written to the DTE bit to halt

transfer. The ACT bit is held to 1 until a block-size transfer completes after 0 is written to the

DTE bit.

In burst mode, transfer is halted after up to three times of EXDMA transfers are performed since

the bus cycle in which 0 is written to the DTE bit has been processed. The ACT bit is held to 1

between termination of the last EXDMA cycle and 0-write in the DTE bit.

(7)

ERRF bit in EDMDR

This bit specifies termination of transfer by EXDMAC clearing the DTE bit to 0 for all channels if

an address error or NMI interrupt is generated. The EXDMAC also sets 1 to the ERRF bit of

EDMDR_0 regardless of the EXDMAC operation to indicate that an address error or NMI

interrupt is generated. However, when an address error or an NMI interrupt has been generated in

EXDMAC module stop mode, the ERRF bit is not set to 1.

(8)

ESIF bit in EDMDR

The ESIF bit in EDMDR is set to 1 when a transfer size interrupt, repeat size end interrupt, or an

extended repeat area overflow interrupt is requested. When the ESIF bit is set to 1 and the ESIE

bit in EDMDR is set to 1, a transfer escape interrupt is requested to the CPU or DTC.

The timing that the ESIF bit is set to 1 is when the EXDMA transfer bus cycle (the source of an

interrupt request) terminates, the ACT bit in EDMDR is set to 0, and transfer is terminated.

When the DTE bit is set to 1 to resume transfer during interrupt processing, the ESIF bit is

automatically cleared to 0 to cancel the interrupt request.

For details on interrupts, see section 11.9, Interrupt Sources.

H8SX/1663R Datenblatt(PDF) 535 Page - Renesas Technology Corp