H8SXSLASH1663R datasheet(536/1504 Pages) RENESAS

536 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 504 of 1468

REJ09B0412-0200

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DTIF bit in EDMDR

The DTIF bit in EDMDR is set to 1 after the data of total transfer size is transferred completely by

EXDMA transfer. When the DTIF bit is set to 1 and the DTIE bit in EDMDR is set to 1, a transfer

end interrupt by the transfer counter is requested to the CPU or DTC.

The timing that the DTIF bit is set to 1 is when the EXDMA transfer bus cycle is terminated, the

ACT bit in EDMDR is set to 0, and the transfer is terminated.

When the DTE bit is set to 1 to resume transfer during interrupt processing, the DTIF bit is

automatically cleared to 0 to cancel the interrupt request.

For details on interrupts, see section 11.9, Interrupt Sources.

11.5.8

Channel Priority Order

The priority order of the EXDMAC channels is: channel 0 > channel 1 > channel 2 > channel 3.

Table 11.6 shows the EXDMAC channel priority order.

Table 11.6

EXDMAC Channel Priority Order

Channel

Channel Priority

Channel 0

Channel 1

Channel 2

Channel 3

High

Low

If transfer requests occur simultaneously for a number of channels, the highest-priority channel

according to the priority order is selected for transfer. Transfer starts after the channel in progress

releases the bus. If a bus request is issued from another bus master other than EXDMAC during a

transfer operation, another bus master cycle is initiated.

Channels are not switched during burst transfer, a block-size transfer in block transfer mode or a

cluster-size transfer in cluster transfer mode.

Figure 11.22 shows an example of the transfer timing when transfer requests occur simultaneously

for channels 0, 1, and 2.

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