H8SXSLASH1663R datasheet(581/1504 Pages) RENESAS

581 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 549 of 1468

REJ09B0412-0200

(3)

Transfer End by Repeat Size End Interrupt

In repeat transfer mode, when the RPTIE bit in EDACR is set to 1 and the next transfer request is

generated on completion of a repeat-size transfer, a repeat size end interrupt request is generated.

The interrupt request terminates EXDMA transfer, the DTE bit in EDMDR is cleared to 0, and the

ESIF bit in EDMDR is set to 1 at the same time. If the DTE bit is set to 1 in this state, transfer

resumes.

In block transfer or cluster transfer mode, a repeat size end interrupt request can be generated. In

block transfer mode, if the next transfer request is generated at the end of a block-size transfer, a

repeat size end interrupt request is generated. In cluster transfer mode, if the next transfer request

is generated at the end of a cluster-size transfer, a repeat size end interrupt request is generated.

(4)

Transfer End by Extended Repeat Area Overflow Interrupt

If an address overflows the extended repeat area when an extended repeat area specification has

been made and the SARIE or DARIE bit in EDACR is set to 1, an extended repeat area overflow

interrupt is requested. The interrupt request terminates EXDMA transfer, the DTE bit in EDMDR

is cleared to 0, and the ESIF bit in EDMDR is set to 1 at the same time.

In dual address mode, if an extended repeat area overflow interrupt is requested during a read

cycle, the following write cycle processing is still executed.

In block transfer mode, if an extended repeat area overflow interrupt is requested during transfer

of a block, transfer continues to the end of the block. Transfer end by means of an extended repeat

area overflow interrupt occurs between block-size transfers.

In cluster transfer mode, if an extended repeat area overflow interrupt is requested during transfer

of a cluster, transfer continues to the end of the cluster. Transfer end by means of an extended

repeat area overflow interrupt occurs between cluster-size transfers.

(5)

Transfer End by 0-Write to DTE Bit in EDMDR

When 0 is written to the DTE bit in EDMDR by the CPU, etc., transfer ends after completion of

the EXDMA cycle in which transfer is in progress or a transfer request was accepted.

In block transfer mode, EXDMA transfer ends after completion of one-block-size transfer in

progress.

In cluster transfer mode, EXDMA transfer ends after completion of one-cluster-size transfer in

progress.

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