H8SXSLASH1663R datasheet(583/1504 Pages) RENESAS

583 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 551 of 1468

REJ09B0412-0200

(8)

Transfer End by Hardware Standby Mode and Reset Input

The EXDMAC is initialized in hardware standby mode and by a reset. EXDMA transfer is not

guaranteed in these cases.

11.8

Relationship among EXDMAC and Other Bus Masters

11.8.1

CPU Priority Control Function Over EXDMAC

The EXDMAC priority level control function can be used for the CPU by setting the CPU priority

control register (CPUPCR). For details, see section 7.7, CPU Priority Control Function Over DTC,

DMAC and EXDMAC.

The EXDMAC priority level can be set independently for each channel by the EDMAP2 to

EDMAP0 bits in EDMDR.

The CPU priority level, which corresponds to the priority level of exception handling, can be set

by updating the values of the CPUP2 to CPUP0 bits in CPUPCR with the interrupt mask bit

values.

When the CPUPCE bit in CPUPCR is set to 1 to enable the CPU priority level control and the

EXDMAC priority level is lower than the CPU priority level, the transfer request of the

corresponding channel is masked and the channel activation is disabled. When the priority level of

another channel is the same or higher than the CPU priority level, the transfer request for another

channel is accepted and transfer is enabled regardless of the priority levels of channels.

The CPU priority level control function holds pending the transfer source, which masked the

transfer request. When the CPU priority level becomes lower than the channel priority level by

updating one of them, the transfer request is accepted and transfer starts. The transfer request held

pending is cleared by writing 0 to the DTE bit.

When the CPUPCE bit is cleared to 0, the lowest CPU priority level is assumed.

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