| Datenblatt-Suchmaschine für elektronische Bauteile |
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H8SX/1663R Datenblatt(PDF) 585 Page - Renesas Technology Corp |
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H8SX/1663R Datenblatt(HTML) 585 Page - Renesas Technology Corp |
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585 / 1504 page ![]() Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Sep. 24, 2008 Page 553 of 1468 REJ09B0412-0200 11.9 Interrupt Sources EXDMAC interrupt sources are a transfer end by the transfer counter, and an escape end interrupt which is caused by the transfer counter not becoming 0. Table 11.7 shows the interrupt sources and their priority order. Table 11.7 Interrupt Sources and Priority Order Interrupt Interrupt Source Interrupt Priority EXDMTEND0 Transfer end indicated by channel 0 transfer counter EXDMTEND1 Transfer end indicated by channel 1 transfer counter EXDMTEND2 Transfer end indicated by channel 2 transfer counter EXDMTEND3 Transfer end indicated by channel 3 transfer counter EXDMEEND0 Channel 0 transfer size error Channel 0 repeat size end Channel 0 source address extended repeat area overflow Channel 0 destination address extended repeat area overflow EXDMEEND1 Channel 1 transfer size error Channel 1 repeat size end Channel 1 source address extended repeat area overflow Channel 1 destination address extended repeat area overflow EXDMEEND2 Channel 2 transfer size error Channel 2 repeat size end Channel 2 source address extended repeat area overflow Channel 2 destination address extended repeat area overflow EXDMEEND3 Channel 3 transfer size error Channel 3 repeat size end Channel 3 source address extended repeat area overflow Channel 3 destination address extended repeat area overflow High Low Interrupt source can be enabled or disabled by setting the DTIE and ESIE bits in EDMDR for the relevant channels. The DTIE bit can be combined with the DTIF bit in EDMDR to generate an EXDMTEND interrupt. The ESIE bit can be combined with the ESIF bit in EDMDR to generate an EXDMEEND interrupt. Interrupt sources in EXDMEEND are not identified as common interrupts. The interrupt priority order among channels is determined by the interrupt controller as shown in table 11.7. For detains see section 7, Interrupt Controller. |
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