H8SXSLASH1663R datasheet(584/1504 Pages) RENESAS

584 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 552 of 1468

REJ09B0412-0200

11.8.2

Bus Arbitration with Another Bus Master

A cycle of another bus master may (or not) be inserted among consecutive EXDMA transfer bus

cycles. The EXDMAC bus mastership can be set so that it is released and transferred to another

bus master.

Some of the consecutive EXDMA transfer bus cycles may be indivisible due to the transfer mode

specification, may be consecutive bus cycles for high-speed access due to the transfer mode

specification, or may be consecutive bus cycles because another bus master does not request the

bus mastership.

These consecutive EXDMA read and write cycles are indivisible: refresh cycle, external bus

release cycle, or external space access cycle by internal bus master (CPU, DTC, DMAC) does not

occur between a read cycle and a write cycle.

In cluster transfer mode, the transfer cycle in one cluster is indivisible.

In block transfer mode and auto-request burst mode, the EXDMA transfer bus cycles continues. In

this period, the bus priority level of the internal bus master is lower than the EXDMAC so that the

external space access is held pending (when EBCCS = 0 in the bus control register 2 (BCR2)).

When switching to another channel, or in the auto-request cycle steal mode, the EXDMA transfer

cycles and internal bus master cycles are alternatively executed. When the internal bus master is

not issuing an external space access cycle, the EXDMA transfer bus cycles are continuously

executed in the allowable range.

When the EBCCS bit in BCR2 is set to 1 to enable the arbitration function between the EXDMAC

and the internal bus master, the bus mastership is released, except for indivisible bus cycles, and

transferred between the EXDMAC and the internal bus master alternatively. For details, see

section 9, Bus Controller (BSC).

H8SX/1663R Datenblatt(PDF) 584 Page - Renesas Technology Corp