H8SXSLASH1663R datasheet(611/1504 Pages) RENESAS

611 / 1504 page

Section 12 Data Transfer Controller (DTC)

Rev. 2.00 Sep. 24, 2008 Page 579 of 1468

REJ09B0412-0200

12.5.3

Transfer Information Writeback Skip Function

By specifying bit SM1 in MRA and bit DM1 in MRB to the fixed address mode, a part of transfer

information will not be written back. This function is performed regardless of short or full address

mode. Table 12.5 shows the transfer information writeback skip condition and writeback skipped

registers. Note that the CRA and CRB are always written back regardless of the short or full

address mode. In addition in full address mode, the writeback of the MRA and MRB are always

skipped.

Table 12.5

Transfer Information Writeback Skip Condition and Writeback Skipped

Registers

SM1

DM1

SAR

DAR

Skipped

Written back

Skipped

Written back

12.5.4

Normal Transfer Mode

In normal transfer mode, one operation transfers one byte, one word, or one longword of data.

From 1 to 65,536 transfers can be specified. The transfer source and destination addresses can be

specified as incremented, decremented, or fixed. When the specified number of transfers ends, an

interrupt can be requested to the CPU.

Table 12.6 lists the register function in normal transfer mode. Figure 12.7 shows the memory map

in normal transfer mode.

Table 12.6

Function

Written Back Value

SAR

Source address

Incremented/decremented/fixed*

DAR

Destination address

Incremented/decremented/fixed*

CRA

Transfer count A

CRA

− 1

CRB

Transfer count B

Not updated

Note:

Transfer information writeback is skipped.

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