H8SXSLASH1663R datasheet(612/1504 Pages) RENESAS

Teilenummer	H8SX/1663R

Bauteilbeschribung	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1504 Pages

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Hersteller	RENESAS [Renesas Technology Corp]

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Section 12 Data Transfer Controller (DTC)

Rev. 2.00 Sep. 24, 2008 Page 580 of 1468

REJ09B0412-0200

SAR

Transfer source data area

DAR

Transfer

Transfer destination data area

Figure 12.7 Memory Map in Normal Transfer Mode

12.5.5

Repeat Transfer Mode

In repeat transfer mode, one operation transfers one byte, one word, or one longword of data. By

the DTS bit in MRB, either the source or destination can be specified as a repeat area. From 1 to

256 transfers can be specified. When the specified number of transfers ends, the transfer counter

and address register specified as the repeat area is restored to the initial state, and transfer is

repeated. The other address register is then incremented, decremented, or left fixed. In repeat

transfer mode, the transfer counter (CRAL) is updated to the value specified in CRAH when

CRAL becomes H'00. Thus the transfer counter value does not reach H'00, and therefore a CPU

interrupt cannot be requested when DISEL = 0.

Table 12.7 lists the register function in repeat transfer mode. Figure 12.8 shows the memory map

in repeat transfer mode.

H8SX/1663R Datenblatt(PDF) 612 Page - Renesas Technology Corp