H8SXSLASH1663R datasheet(615/1504 Pages) RENESAS

615 / 1504 page

Section 12 Data Transfer Controller (DTC)

Rev. 2.00 Sep. 24, 2008 Page 583 of 1468

REJ09B0412-0200

12.5.7

Chain Transfer

Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed

consecutively in response to a single transfer request. Setting the CHNE and CHNS bits in MRB

set to 1 enables a chain transfer only when the transfer counter reaches 0. SAR, DAR, CRA, CRB,

MRA, and MRB, which define data transfers, can be set independently. Figure 12.10 shows the

chain transfer operation.

In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the

end of the specified number of transfers or by setting the DISEL bit to 1, and the interrupt source

flag for the activation source and DTCER are not affected.

In repeat transfer mode, setting the RCHNE bit in DTCCR and the CHNE and CHNS bits in MRB

to 1 enables a chain transfer after transfer with transfer counter = 1 has been completed.

Transfer information

CHNE = 1

Transfer information

CHNE = 0

Transfer information

stored in user area

Data area

Transfer source data (1)

Transfer destination data (1)

Transfer source data (2)

Transfer destination data (2)

Transfer information

start address

Vector table

DTC vector

address

Figure 12.10 Operation of Chain Transfer

H8SX/1663R Datenblatt(PDF) 615 Page - Renesas Technology Corp