H8SXSLASH1663R datasheet(614/1504 Pages) RENESAS

614 / 1504 page

Section 12 Data Transfer Controller (DTC)

Rev. 2.00 Sep. 24, 2008 Page 582 of 1468

REJ09B0412-0200

12.5.6

Block Transfer Mode

In block transfer mode, one operation transfers one block of data. Either the transfer source or the

transfer destination is designated as a block area by the DTS bit in MRB.

The block size is 1 to 256 bytes (1 to 256 words, or 1 to 256 longwords). When the transfer of one

block ends, the block size counter (CRAL) and address register (SAR when DTS = 1 or DAR

when DTS = 0) specified as the block area is restored to the initial state. The other address register

is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. When

the specified number of transfers ends, an interrupt is requested to the CPU.

Table 12.8 lists the register function in block transfer mode. Figure 12.9 shows the memory map

in block transfer mode.

Table 12.8

Written Back Value

SAR

Source address

DTS =0: Incremented/decremented/fixed*

DTS = 1: SAR initial value

DAR

Destination address

DTS = 0: DAR initial value

DTS =1: Incremented/decremented/fixed*

CRAH

Block size storage

CRAH

CRAL

Block size counter

CRAH

CRB

Block transfer counter

CRB

− 1

Note:

Transfer information writeback is skipped.

Transfer source data area

Transfer destination data area

(specified as block area)

Block area

DAR

SAR

Transfer

1st block

Nth block

Figure 12.9 Memory Map in Block Transfer Mode

(When Transfer Destination is Specified as Block Area)

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