H8SXSLASH1663M datasheet(503/1504 Pages) RENESAS

503 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 471 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

value

R/W

Description

ESIE

R/W

Transfer Escape Interrupt Enable

Enables or disables a transfer escape end interrupt

request occurred during EXDMA transfer. When this bit

is set to 1, and the ESIF bit is set to 1, a transfer

escape end interrupt is requested to the CPU or DTC.

The transfer escape end interrupt request is canceled

by clearing this bit or the ESIF bit to 0.

0: Transfer escape interrupt request disabled

1: Transfer escape interrupt request enabled

DTIE

R/W

Data Transfer Interrupt Enable

Enables or disables a transfer end interrupt request by

the transfer counter. When this bit is set to 1 and the

DTIF bit is set to 1, a transfer end interrupt is requested

to the CPU or DTC. The transfer end interrupt request

is canceled by clearing this bit or the DTIF bit to 0.

0: Transfer end interrupt request disabled

1: Transfer end interrupt request enabled

DTF1

DTF0

R/W

Data Transfer Factor 1 and 0

Selects a source to activate EXDMAC. For external

requests, a sampling method is selected by the

EDREQS bit.

00: Auto-request (cycle steal mode)

01: Auto-request (burst mode)

10: Setting prohibited

11: External request



R/W

Reserved

The initial value should not be changed.

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