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H8SX/1663M Datenblatt(PDF) 506 Page - Renesas Technology Corp

Teilenummer H8SX/1663M
Bauteilbeschribung  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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Hersteller  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663M Datenblatt(HTML) 506 Page - Renesas Technology Corp

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Section 11 EXDMA Controller (EXDMAC)
Rev. 2.00 Sep. 24, 2008 Page 474 of 1468
REJ09B0412-0200
Bit
Bit Name
Initial
value
R/W
Description
29 to 27
All 0
R
Reserved
They are always read as 0 and cannot be modified.
26
RPTIE
0
R/W
Repeat Size End Interrupt Enable
Enables or disables a repeat size end interrupt request.
When this bit is set to 1 and the next transfer source is
generated at the end of a repeat-size transfer in repeat
transfer mode, the DTE bit in EDMDR is cleared to 0. At
the same time, the ESIF bit in EDMDR is set to 1 to
indicate that a repeat size end interrupt is requested.
Even if the repeat area is not specified (ARS1, ARS0 =
B'10), the repeat size end interrupt can be requested at
the end of a repeat-size transfer.
When this bit is set to 1 and the next transfer source is
generated at the end of a block- or cluster-size transfer
in block transfer or cluster transfer mode, the DTE bit in
EDMDR is cleared to 0. At the same time, the ESIF bit
in EDMDR is set to 1 to indicate that the repeat size
end interrupt is requested.
0: Repeat size end interrupt request disabled
1: Repeat size end interrupt request enabled
25
24
ARS1
ARS0
0
0
R/W
R/W
Area Select 1 and 0
Select the block area or repeat area in block transfer,
repeat transfer or cluster transfer mode.
00: Block area/repeat area on the source address side
01: Block area/repeat area on the destination address
side
10: Block area/repeat area not specified
11: Setting prohibited
23, 22
All 0
R
Reserved
They are always read as 0 and cannot be modified.



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