LTC4261IGN datasheet(14/32 Pages) LINER

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LTC4261/LTC4261-2

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If any of the above conditions is violated before the start-up

delay expires, CTMR is quickly discharged and the turn-on

sequence is restarted. After all the conditions are validated

throughout the start-up delay, the ON pin is then checked.

If it is high, the FET will be turned on. Otherwise, the FET

will be turned on when the ON pin is raised high or the FET

ON bit D3 in the CONTROL register is set to “1” through

the I2C interface.

The FET turn-on sequence follows by charging an external

capacitor at the SS pin (CSS) with a 10µA pull-up current

and the voltage at SS (VSS) is converted to a current

(IGATE(UP)) of 11.5µA· VSS/2.56V for GATE pull-up. When

the GATE reaches the FET threshold voltage, the inrush

current starts to ﬂow through the FET and a current

(IRAMP) of 20µA· VSS/2.56V ﬂows out of the RAMP pin

and through an external capacitor (CR) connected between

RAMP and VOUT. The SS voltage is clamped to 2.56V, which

corresponds to IGATE(UP) = 11.5µA and IRAMP = 20µA. The

RAMP pin voltage is regulated at 1.1V and the ramp rate

of VOUT determines the inrush current:

IµA

INRUSH

= 20 •

The ramp rate of VSS determines dI/dt of the inrush

current:

µA

µF

ms C

INRUSH

RSS

= 20

256

••

•

If CSS is absent, an internal circuit pulls the SS pin from

0V to 2.56V in about 220µs.

When VOUT is ramped down to VEE, IGATE returns to

the GATE pin and pulls the GATE up to VGATEH. Figure 3

illustrates the start-up sequence of the LTC4261/

LTC4261-2.

During board insertion and input power step, an internal

clamp turns on to hold the RAMP pin low. Capacitor CF

and resistor RF suppress the noise at the RAMP pin. For

proper operation, RF • CR should not exceed 50µs. The

recommended value of CF is 3 • CR.

Power Good Monitors

When VDS of the pass transistor falls below 1.77V and

GATE pulls above VZ – 1.2V, an internal power good

signal is latched and a series of three delay cycles are

started as shown in Figure 3. When the ﬁrst delay cycle

with a duration of 2tD expires, the PG pin pulls low as a

power good signal to turn on the ﬁrst module. When the

second delay cycle (2tD) expires, the PGIO pin pulls low

as a power good signal to turn on the second module. The

third delay cycle with a duration of 4tD is for PGI check.

Before the third delay cycle expires, the PGI pin must be

pulled low by an external supply monitor (such as the

LTC2900 in Figure 2) to keep the FET on. Otherwise, the

FET is turned off and the power bad fault (PBAD) is logged

in the FAULT register. The 2tD timer delay is obtained by

charging CTMR with a 5µA current and discharging CTMR

with a 12mA current when TMR reaches 2.56V. For the

4tD timer delay, the charging and discharging currents of

CTMR are both 5µA. The power good signals at PG and

PGIO are reset in all FET turn-off conditions except the

overvoltage fault.

Turn-Off Sequence and Auto-Retry

In any of the following conditions, the FET is turned off

by pulling down GATE with a 110mA current, and CSS

and CTMR are discharged with 12mA currents.

1. The ON pin is low or the ON bit in the CONTROL reg-

ister is set to 0.

2. The EN pin is high.

3. The voltage at UVL is lower than 2.291V and the volt-

age at UVH is lower than 2.56V (undervoltage fault).

4. The voltage at OV is higher than 1.77V (overvoltage

fault).

5. The voltage at VIN is lower than 9V (VIN undervoltage

lockout).

APPLICATIONS INFORMATION

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