LTC4261IGN datasheet(16/32 Pages) LINER

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LTC4261/LTC4261-2

42612fb

EN and ON

Figure 4 shows a logic diagram for EN and ON as they

relate to GATE, ALERT and internal registers A4, A7, B4,

C4 and D3. Also affecting GATE is the status of UV, OV

and several other fault conditions. The EN and ON pins

have 0.8V to 2V logic thresholds relative to VEE with a

maximum input leakage current of ±2µA.

is set high whenever EN changes state. Rising and falling

edges at the ON pin set and clear FET-on control bit, D3.

Another path allows a falling edge at EN to latch a high

state at the ON pin (such as when ON is permanently

pulled high) into D3 after a time delay. Both B4 and D3

can be set or cleared directly by I2C, and both are cleared

low whenever INTVCC drops below its UVLO threshold.

The condition of the GATE pin output is controlled by

sence of UV, OV and other faults.

Overcurrent Protection and Overcurrent Fault

The LTC4261/LTC4261-2 feature two levels of protec-

tion from short-circuit and overcurrent conditions. Load

current is monitored by the SENSE pin and resistor

RS. There are two distinct thresholds for the voltage at

SENSE: 50mV for engaging the active current limit loop

and starting a 530µs circuit breaker timer and 150mV for

a fast GATE pull-down to limit peak current in the event

of a catastrophic short circuit or an input step.

In an overcurrent condition, when the voltage drop across

RS exceeds 50mV, the current limit loop is engaged and

an internal 530µs circuit breaker timer is started. The

current limit loop servos the GATE to maintain a constant

output current of 50mV/RS. When the circuit breaker

timer expires, the FET is turned off by pulling GATE down

with a 110mA current, the capacitors at SS and TMR are

discharged and the power good signals are reset. At this

time, the overcurrent present bit A2 and the overcurrent

fault bit B2 are set, and the circuit breaker timer is reset.

After the FET is turned off, the overcurrent present bit

A2 is cleared. If the overcurrent auto-retry bit D2 has

been set, the FET will turn on again automatically after

a cooling time of 4tD. Otherwise, the FET will remain off

until the overcurrent fault bit B2 is reset. When the over-

current fault bit is reset (see Resetting Faults), the FET

is allowed to turn on again after a delay of 4tD. The 4tD

cooling time associated with the overcurrent fault will not

be interrupted by any other fault condition. See Figure 5

for operation of LTC4261/LTC4261-2 under overcurrent

condition followed by auto-retry.

R/W

I2C

CLR

R/W

CLR

INTVCC UVLO

ABSENCE OF UV/OV AND OTHER FAULTS

CLR

1 tD

TIMER

DELAY

EDGE

DETECTOR

STATE-CHANGE

DETECTOR

ALERT*

GATE ON

ALERT

42612 F04

READ ANY REGISTER

*B4 • C4 IS ONE OF SEVEN CONDITIONS

THAT CAN GENERATE AN ALERT OUTPUT.

SEE TABLE 5

I2C ALERT RESPONSE

Figure 4. Logic Block Diagram of EN and ON Pins

APPLICATIONS INFORMATION

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