LTC1749 datasheet(12/20 Pages) LINER

12 / 20 page

LTC1749

1749f

In operation, the ADC quantizes the input to the stage and

the quantized value is subtracted from the input by the

DAC to produce a residue. The residue is amplified and

output by the residue amplifier. Successive stages operate

out of phase so that when the odd stages are outputting

their residue, the even stages are acquiring that residue

and visa versa.

When ENC is low, the analog input is sampled differentially

directly onto the input sample-and-hold capacitors, inside

the “Input S/H” shown in the block diagram. At the instant

that ENC transitions from low to high, the sampled input

is held. While ENC is high, the held input voltage is

buffered by the S/H amplifier which drives the first pipelined

ADC stage. The first stage acquires the output of the S/H

during this high phase of ENC. When ENC goes back low,

the first stage produces its residue which is acquired by

the second stage. At the same time, the input S/H goes

back to acquiring the analog input. When ENC goes back

high, the second stage produces its residue which is

acquired by the third stage. An identical process is re-

peated for the third stage, resulting in a third stage residue

that is sent to the fourth stage ADC for final evaluation.

Each ADC stage following the first has additional range to

accommodate flash and amplifier offset errors. Results

from all of the ADC stages are digitally synchronized such

that the results can be properly combined in the correction

logic before being sent to the output buffer.

SAMPLE/HOLD OPERATION AND INPUT DRIVE

Sample/Hold Operation

Figure 2 shows an equivalent circuit for the LTC1749

CMOS differential sample-and-hold. The differential ana-

log inputs are sampled directly onto sampling capacitors

(CSAMPLE) through NMOS switches. This direct capacitor

sampling results in lowest possible noise for a given

sampling capacitor size. The capacitors shown attached to

each input (CPARASITIC) are the summation of all other

capacitance associated with each input.

During the sample phase when ENC/ENC is low, the NMOS

switch connects the analog inputs to the sampling capaci-

tors and they charge to, and track the differential input

voltage. When ENC/ENC transitions from low to high the

sampled input voltage is held on the sampling capacitors.

During the hold phase when ENC/ENC is high the sampling

capacitors are disconnected from the input and the held

voltage is passed to the ADC core for processing. As

ENC/ENC transitions from high to low the inputs are

reconnected to the sampling capacitors to acquire a new

sample. Since the sampling capacitors still hold the previ-

ous sample, a charging glitch proportional to the change

in voltage between samples will be seen at this time. If the

change between the last sample and the new sample is

small the charging glitch seen at the input will be small. If

the input change is large, such as the change seen with

input frequencies near Nyquist, then a larger charging

glitch will be seen.

Common Mode Bias

The ADC sample-and-hold circuit requires differential drive

to achieve specified performance. Each input should swing

within the valid input range, around a common mode volt-

age of 2.0V. The VCM output pin (Pin 2) may be used to pro-

vide the common mode bias level. VCM can be tied directly

to the center tap of a transformer to set the DC input level

or as a reference level to an op amp differential driver cir-

cuit. The VCM pin must be bypassed to ground close to the

ADC with a 4.7

µF or greater capacitor.

APPLICATIO S I FOR ATIO

Figure 2. Equivalent Input Circuit

CSAMPLE

3.5pF

RON

Ω

RON

Ω

VDD

LTC1749

AIN

1749 F02

CSAMPLE

3.5pF

BIAS

VDD

AIN

–

ENC

CPARASITIC

2.4pF

CPARASITIC

1pF

CPARASITIC

1pF

CPARASITIC

2.4pF

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