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LTC1749

1749f

Maximum and Minimum Encode Rates

The maximum encode rate for the LTC1749 is 80Msps. For

the ADC to operate properly the encode signal should have

a 50% (

±4%) duty cycle. Each half cycle must have at least

6ns for the ADC internal circuitry to have enough settling

time for proper operation. Achieving a precise 50% duty

cycle is easy with differential sinusoidal drive using a

transformer or using symmetric differential logic such as

PECL or LVDS. When using a single-ended encode signal

asymmetric rise and fall times can result in duty cycles that

are far from 50%.

At sample rates slower than 80Msps the duty cycle can

vary from 50% as long as each half cycle is at least 6ns.

The lower limit of the LTC1749 sample rate is determined

by droop of the sample-and-hold circuits. The pipelined

APPLICATIO S I FOR ATIO

architecture of this ADC relies on storing analog signals on

small valued capacitors. Junction leakage will discharge

the capacitors. The specified minimum operating fre-

quency for the LTC1749 is 1Msps.

DIGITAL OUTPUTS

Digital Output Buffers

Figure 9 shows an equivalent circuit for a single output

buffer. Each buffer is powered by OVDD and OGND, iso-

lated from the ADC power and ground. The additional

N-channel transistor in the output driver allows operation

down to low voltages. The internal resistor in series with

the output makes the output appear as 50

Ω to external

circuitry and may eliminate the need for external damping

resistors.

Figure 7. Transformer Driven ENC/ENC

Figure 8a. Single-Ended ENC Drive,

Not Recommended for Low Jitter

Figure 8b. ENC Drive Using a CMOS-to-PECL Translator

VDD

LTC1749

1749 F07

BIAS

VDD

ENC

ANALOG INPUT

2V BIAS

1:4

0.1

µF

CLOCK

INPUT

Ω

TO INTERNAL

ADC CIRCUITS

1749 F08a

ENC

VTHRESHOLD = 2V

ENC

0.1

µF

LTC1749

1749 F08b

ENC

130

Ω

3.3V

130

Ω

MC100LVELT22

LTC1749

Ω

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