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LTC1749 Datenblatt(PDF) 18 Page - Linear Technology |
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LTC1749 Datenblatt(HTML) 18 Page - Linear Technology |
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18 / 20 page ![]() 18 LTC1749 1749f sheet. Bypass capacitors must be located as close to the pins as possible. Of particular importance are the capaci- tors between REFHA and REFLB and between REFHB and REFLA. These capacitors should be as close to the device as possible (1.5mm or less). Size 0402 ceramic capacitors are recomended. The large 4.7 µFcapacitorbetweenREFHA and REFLA can be somewhat further away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC1749 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. An analog ground plane separate from the digital process- ing system ground should be used. All ADC ground pins labeled GND should connect to this plane. All ADC VDD bypass capacitors, reference bypass capacitors and input filter capacitors should connect to this analog plane. The LTC1749 has three output driver ground pins, labeled OGND (Pins 27, 38 and 47). These grounds should con- nect to the digital processing system ground. The output driver supply, OVDD should be connected to the digital processing system supply. OVDD bypasscapacitorsshould bypass to the digital system ground. The digital process- ing system ground should be connected to the analog plane at ADC OGND (Pin 38). HEAT TRANSFER Most of the heat generated by the LTC1749 is transferred from the die through the package leads onto the printed circuit board. In particular, ground pins 12, 13, 36 and 37 are fused to the die attach pad. These pins have the lowest thermal resistance between the die and the outside envi- ronment. It is critical that all ground pins are connected to a ground plane of sufficient area. The layout of the evalu- ation circuit shown on the following pages has a low ther- mal resistance path to the internal ground plane by using multiple vias near the ground pins. A ground plane of this size results in a thermal resistance from the die to ambient of 35 °C/W.Smallerareagroundplanesorpoorlyconnected ground pins will result in higher thermal resistance. APPLICATIO S I FOR ATIO |
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