TLC5540

SLAS105D − JANUARY 1995 − REVISED APRIL 2004

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11

PRINCIPLES OF OPERATION

functional description

The TLC5540 uses a modified semiflash architecture as shown in the functional block diagram. The four most

significant bits (MSBs) of every output conversion result are produced by the upper comparator block CB1. The

four least significant bits (LSBs) of each alternate output conversion result are produced by the lower

comparator blocks CB-A and CB-B in turn (see Figure 12).

The reference voltage that is applied to the lower comparator resistor string is one sixteenth of the amplitude

of the refence applied to the upper comparator resistor string. The sampling comparators of the lower

comparator block require more time to sample the lower voltages of the reference and residual input voltage.

By applying the residual input voltage to alternate lower comparator blocks, each comparator block has twice

as much time to sample and convert as would be the case if only one lower comparator block were used.

VI(1)

VI(2)

VI(3)

VI(4)

CLK1

CLK2

CLK3

CLK4

S(1)

C(1)

S(2)

C(2)

S(3)

C(3)

S(4)

C(4)

S(1)

H(1)

C(1)

S(3)

H(3)

C(3)

H(0)

C(0)

S(2)

H(2)

C(2)

S(4)

H(4)

LD(−2)

OUT(−2)

OUT(−1)

OUT(0)

OUT(1)

ANALOG IN

(Sampling Points)

CLK (Clock)

Upper Comparators Block (CB1)

Upper Data

Lower Reference Voltage

Lower Comparators Block (CB-A)

Lower Data (A)

Lower Comparators Block (CB-B)

Lower Data (B)

D1 −D8 (Data Output)

UD(0)

RV(0)

UD(1)

RV(1)

UD(2)

RV(2)

UD(3)

RV(3)

LD(−1)

LD(0)

LD(1)

LD(2)

tpd

Figure 12. Internal Functional Timing Diagram

This conversion scheme, which reduces the required sampling comparators by 30 percent compared to

standard semiflash architectures, achieves significantly higher sample rates than the conventional semiflash

conversion method.