TLC5540

SLAS105D − JANUARY 1995 − REVISED APRIL 2004

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12

PRINCIPLES OF OPERATION

functional description (continued)

The MSB comparator block converts on the falling edge of each applied clock cycle. The LSB comparator blocks

CB-A and CB-B convert on the falling edges of the first and second following clock cycles, respectively. The

timing diagram of the conversion algorithm is shown in Figure 12.

analog input operation

The analog input stage to the TLC5540 is a chopper-stabilized comparator and is equivalently shown below:

VDDA

ANALOG IN

S1

Vref(N)

φ1

φ2

φ2

S3

φ1

Cs

To Encoder Logic

φ2

S2

φ1

Cs

To Encoder Logic

φ2

S(N)

φ1

Cs

To Encoder Logic

Figure 13. External Connections for Using the Internal Reference Resistor Divider

Figure 13 depicts the analog input for the TLC5540. The switches shown are controlled by two internal clocks,

φ1 and φ2. These are nonoverlapping clocks that are generated from the CLK input. During the sampling period,

period, S2 through S(N) are closed. This sets the comparator input to approximately 2.5 V. The delta voltage

0. The small resistance values for the switch, S1, and small value of the sampling capacitor combine to produce

the wide analog input bandwidth of the TLC5540. The source impedance driving the analog input of the

TLC5540 should be less than 100

Ω across the range of input frequency spectrum.

reference inputs − REFB, REFT, REFBS, REFTS

The range of analog inputs that can be converted are determined by REFB and REFT, REFT being the

maximum reference voltage and REFB being the minimum reference voltage. The TLC5540 is tested with

REFT = 2.6 V and REFB = 0.6 V producing a 2-V full-scale range. The TLC5540 can operate with

REFT − REFB = 5 V, but the power dissipation in the reference resistor increases significantly (93 mW

nominally). It is recommended that a 0.1

µF capacitor be attached to REFB and REFT whether using externally

or internally generated voltages.