TMS320VC33 datasheet(14/57 Pages) TI

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TMS320VC33

DIGITAL SIGNAL PROCESSOR

SPRS087E − FEBRUARY 1999 − REVISED JANUARY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PLL isolation

The internal PLL supplies can be directly connected to CVDD and VSS (0 Ω case), partially isolated as shown

in Figure 5, or fully isolated as shown in Figure 6. The RC network prevents the PLL supplies from turning high

frequency noise in the CVDD and VSS supplies into jitter.

CVDD

0 −100

Ω

0.1

µF

0.01

µF

0 −100

Ω

VSS

PLLVDD

PLLVSS

Figure 6. PLL Isolation Circuit Diagram

clock and PLL considerations on initialization

On power up, the CPU clock divide mode can be in MAXSPEED, LOPOWER or IDLE2, or the PLL could be

in an undefined mode. RESET falling in the presence of a valid CPU clock is used to clear this state, after which

the device will synchronously terminate any external activity.

The 5x Fclkin PLL of the TMS320VC33 contains an 8-bit PLL−LOCK counter which causes the PLL to output

a frequency of Fclkin/2 during the initial ramp. This counter, however, does not increment while RESET is low

or in the absence of an input clock. A minimum of 256 input clocks are required before the first falling edge of

reset for the PLL to output to clear this counter. The setup and behavior that is seen is as follows.

Power is applied to the DSP with RESET low and the input clock high or low. A clock is applied (RESET is still

low) and the PLL appears to lock on to the input clock, producing the expected x5 output frequency. RESET

is driven high and the PLL output immediately drops to Fclkin/2 for 0-256 input cycles or 128 of the Fclkin/2

output cycles. The PLL/CPU clock then switches to x5 mode.

The switch over is synchronous and does not create a clock glitch, so the only effect is that the CPU runs slow

for up to the first 128 cycles after reset goes high. Once the PLL has stabilized, the counter will remain cleared

and subsequent resets will not exhibit this condition.

Systems that are not using the crystal oscillator may be required to supply a current of 250mA per DSP if full

power is applied with no clock source. This extra current condition is a result of uninitialized internal logic within

the DSP core and is corrected when the CPU sees a minimum of four internal clocks. The crystal oscillator is

typically immune to this condition since the oscilator and core circuitry become semi-functional at CVDD = 1 V

where the fault current is considerably lower. An alternate clock pulse can also be applied to either the EXTCLK

or XIN clock input pins.

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