TMS320VC33 datasheet(21/57 Pages) TI

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TMS320VC33

DIGITAL SIGNAL PROCESSOR

SPRS087E − FEBRUARY 1999 − REVISED JANUARY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

designing your target system’s emulator connector (14-pin header) (continued)

Although you can use other headers, recommended parts include:

straight header, unshrouded

DuPont Connector Systems

part numbers:

65610−114

65611−114

67996−114

67997−114

JTAG emulator cable pod logic

Figure 12 shows a portion of the emulator cable pod. The functional features of the pod are as follows:

D Signals TDO and TCK_RET can be parallel-terminated inside the pod if required by the application. By

default, these signals are not terminated.

D Signal TCK is driven with a 74LVT240 device. Because of the high-current drive (32 mA IOL/IOH), this signal

can be parallel-terminated. If TCK is tied to TCK_RET, the parallel terminator in the pod can be used.

D Signals TMS and TDI can be generated from the falling edge of TCK_RET, according to the IEEE 1149.1

bus slave device timing rules.

D Signals TMS and TDI are series-terminated to reduce signal reflections.

D A 10.368-MHz test clock source is provided. You may also provide your own test clock for greater flexibility.

100

TL7705A

RESIN

270

JP2

180

TCK_RET (Pin 9){

EMU1 (Pin 14)

EMU0 (Pin 13)

74AS1034

GND (Pins 4,6,8,10,12)

TRST (Pin 2)

TCK (Pin 11){

10.368 MHz

TDI (Pin 3)

TMS (Pin 1)

TDO (Pin 7)

74LVT240

180

JP1

270

74F175

PD(VCC) (Pin 5)

+5 V

74AS1004

† The emulator pod uses TCK_RET as its clock source for internal synchronization. TCK is provided as an optional target system

test clock source.

Figure 12. JTAG Emulator Cable Pod Interface

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