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CY7C024/024A/0241
CY7C025/0251
Document #: 38-06035 Rev. *D
Page 16 of 21
Figure 15. Interrupt Timing Diagrams
Notes
43. tHA depends on which enable pin (CEL or R/WL) is deasserted first.
44. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
Switching Waveforms (continued)
WRITE FFF (1FFF CY7C025)
tWC
Right Side Clears INTR :
tHA
READ FFF
tRC
tINR
WRITE FFE (1FFE CY7C025)
tWC
Right Side Sets INTL:
Left Side Sets INTR :
Left Side Clears INT L:
READ FFE
tINR
tRC
ADDRESSR
CE L
R/W L
INT L
OE L
ADDRESSR
R/WR
CE R
INTL
ADDRESSR
CER
R/WR
INTR
OE R
ADDRESSL
R/WL
CE L
INTR
tINS
tHA
tINS
(1FFF CY7C025)
(1FFE CY7C025)
[43]
[44]
[44]
[44]
[43]
[44]
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