CS8422_09 datasheet(17/82 Pages) CIRRUS

17 / 82 page

DS692PP2

CS8422

SWITCHING SPECIFICATIONS

Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF.

Parameter

Symbol

Min

Typ

Max

Units

RST pin Low Pulse Width (Note 7)

PLL Clock Recovery Sample Rate Range (Note 8)

216

kHz

RMCK Output Jitter (Note 9)

Differential RX Mode

Single-Ended RX Mode

200

475

ps RMS

RMCK Output Duty Cycle

XTI Frequency

Crystal

27.000

MHz

Digital Clock Source

1.024

49.152

MHz

XTI Pulse Width High/Low

MCLK_OUT Duty Cycle

VL = 3.3V, 5V

RMCK Output Frequency

49.152

MHz

MCLK_OUT Frequency

49.152

MHz

Slave Mode

ISCLK Frequency

49.152

MHz

ISCLK High Time

tsckh

9.2

ISCLK Low Time

tsckl

9.2

OSCLK Frequency

26.9

MHz

OSCLK High Time

tsckh

16.7

OSCLK Low Time

tsckl

16.7

I/OLRCK Edge to I/OSCLK Rising Edge

tlcks

5.7

I/OSCLK Rising Edge to I/OLRCK Edge

tlckd

4.2

OSCLK Falling Edge/OLRCK Edge to SDOUT Output

Valid

tdpd

13.7

SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge

tds

2.2

SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge

tdh

5.5

TDM Mode OLRCK High Time (Note 10)

tlrckh

TDM Mode OLRCK Rising Edge to OSCLK Rising Edge

tfss

5.3

TDM Mode OSCLK Rising Edge to OLRCK Falling Edge

tfsh

4.2

Master Mode

I/OSCLK Frequency (non-TDM Mode)

48*Fsi/o

128*Fsi/o

MHz

I/OLRCK Duty Cycle

49.5

50.5

I/OSCLK Duty Cycle

I/OSCLK Falling Edge to I/OLRCK Edge

tlcks

4.2

OSCLK Falling Edge to SDOUT Output Valid

tdpd

4.6

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