CS8422_09 datasheet(41/82 Pages) CIRRUS

41 / 82 page

DS692PP2

CS8422

determines what the output sample rate will be based on the MCLK selected for SDOUT1, as shown in the

hardware control pin descriptions shown above. For SDOUT2, the output sample rate is dictated by the in-

coming AES3 data, and the master mode clock ratio determines the frequency of RMCK relative to the in-

coming AES3 sample rate. Note: if TDM Mode is selected for SDOUT1, then SDOUT1 cannot be set to

“Master, Fso = MCLK/128”.

SAOF pin

SDOUT1 Data Format

SDOUT2 Data Format

32.4 k

Ω ± 1% to GND

I²S 24-bit data

I²S

16.2 k

Ω ± 1% to GND

I²S 20-bit data

I²S

8.06 k

Ω ± 1% to GND

I²S 16-bit data

I²S

4.02 k

Ω ± 1% to GND

Left-Justified 24-bit data

Left-Justified

1.96 k

Ω ± 1% to GND

Left-Justified 20-bit data

Left-Justified

≤1.0 kΩ + 1% to GND

Left-Justified 16-bit data

Left-Justified

32.4 k

Ω ± 1% to VL

Right-Justified 24-bit data

(Master mode only)

Right-Justified

(Master mode only)

16.2 k

Ω ± 1% to VL

Right-Justified 20-bit data

(Master mode only)

Right-Justified

(Master mode only)

8.06 k

Ω ± 1% to VL

Right-Justified 16-bit data

(Master mode only)

Right-Justified

(Master mode only)

4.02 k

Ω ± 1% to VL

TDM Mode 24-bit data

I²S

1.96 k

Ω ± 1% to VL

TDM Mode 20-bit data

I²S

≤1.0 kΩ + 1% to VL

TDM Mode 16-bit data

I²S

Table 4. Hardware Mode Serial Audio Format Control

MS_SEL pin

SDOUT1

SDOUT2

127.0 k

Ω ± 1% to GND

Slave

RMCK = 256 x Fsi

63.4 k

Ω ± 1% to GND Master, Fso = MCLK/128

32.4 k

Ω ± 1% to GND Master, Fso = MCLK/256

16.2 k

Ω ± 1% to GND Master, Fso = MCLK/512

8.06 k

Ω ± 1% to GND

Slave

Master Mode,

RMCK = 128 x Fsi

4.02 k

Ω ± 1% to GND Master, Fso = MCLK/128

1.96 k

Ω ± 1% to GND Master, Fso = MCLK/256

≤1.0 kΩ + 1% to GND Master, Fso = MCLK/512

127.0 k

Ω ± 1% to VL

Slave

Master Mode,

RMCK = 256 x Fsi

63.4 k

Ω ± 1% to VL

Master, Fso = MCLK/128

32.4 k

Ω ± 1% to VL

Master, Fso = MCLK/256

16.2 k

Ω ± 1% to VL

Master, Fso = MCLK/512

8.06 k

Ω ± 1% to VL

Slave

Master Mode,

RMCK = 512 x Fsi

4.02 k

Ω ± 1% to VL

Master, Fso = MCLK/128

1.96 k

Ω ± 1% to VL

Master, Fso = MCLK/256

≤1.0 kΩ + 1% to VL

Master, Fso = MCLK/512

Table 5. Hardware Mode Serial Audio Port Clock Control

CS8422 Datenblatt(PDF) 41 Page - Cirrus Logic

CS8422 Datenblatt(HTML) 41 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

Datenblatt Download

Link URL