CS8422_09 datasheet(25/82 Pages) CIRRUS

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DS692PP2

CS8422

5.1

Serial Port Clock Operation

5.1.1

Master Mode

When a serial port is set to master mode, its left/right clock (ILRCK, OLRCK1, or OLRCK2), and its serial

bit-clock (ISCLK, OSCLK1, or OSCLK2) are outputs. If a serial output is sourced directly by the AES3 re-

ceiver, then that serial port’s left/right clock and serial bit-clock will be synchronous with RMCK. If a serial

port is routed to or from the sample rate converter (SRC), then that serial port’s left/right clock and serial

bit-clock can be synchronous with either the XTI-XTO or RMCK when it is in master mode.

If a serial output is source directly by the serial input port without the use of the SRC, then all associated

clocks must be synchronous, so both serial ports must use the same master clock source. It is for this

reason that, when in this mode, the serial output clock control is done through the Serial Audio Input Clock

Control (07h) register.

5.1.2

Slave Mode

When a serial port is in slave mode, its left/right clock (ILRCK, OLRCK1, or OLRCK2), and its serial bit-

clock (ISCLK, OSCLK1, or OSCLK2) are inputs. If the serial input or a serial output has the SRC in its

data path, then the serial port’s LRCK and SCLK may be asynchronous to all other serial ports. The

left/right clock should be continuous, but the duty cycle can be less than 50% if enough serial clocks are

present in each associated LRCK phase to clock all of the data bits.

If there are fewer SCLK periods than required to clock all the bits present in one half LRCK period in Left-

Justified and I²S Modes, data will be truncated beginning with the LSB. In Right-Justified Modes, the data

will be invalid.

If a serial audio output is operated in slave mode and sourced directly by the AES3 receiver or the serial

input port without the use of the sample rate converter, then the OLRCK supplied to the serial audio output

should be synchronous to Fsi or ILRCK to avoid skipped or repeated samples. The OSLIP bit (“Interrupt

Status (14h)” on page 59) is provided to indicate when skipped or repeated samples occur.

If the input sample rate, Fsi or ILRCK, is greater than the slave-mode OLRCK frequency, then dropped

samples will occur. If Fsi or ILRCK is less than the slave-mode OLRCK frequency, then samples will be

repeated. In either case the OSLIP bit will be set to 1 and will not be cleared until read through the control

port.

5.1.3

Hardware Mode Control

In Hardware Mode, the serial audio input port is not available. SDOUT1 is the serial data output from the

sample rate converter, and SDOUT2 is the serial audio output directly from the AES3-compatible receiver.

Because there is no serial audio input available in Hardware Mode, all audio data input is done through

the AES3-compatible receiver. In Hardware Mode, the serial output ports are controlled through the SAOF

and MS_SEL pins. See “Hardware Mode Serial Audio Port Control” on page 40 for more details.

In Hardware Mode, there are always 64 SCLK periods per LRCK period when a serial port is set to master

mode.

5.1.4

Software Mode Control

In Software Mode, the CS8422 provides a serial audio input port and two serial audio output ports. Each

serial port’s clocking and data routing options are fully configurable as shown in Serial Audio Input Data

Format (0Bh), Serial Audio Output Data Format - SDOUT1 (0Ch), and Serial Audio Output Data Format

- SDOUT2 (0Dh) registers, found on pages 53, 54, and 55.

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