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TLE8262E Datenblatt(PDF) 61 Page - Infineon Technologies AG |
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TLE8262E Datenblatt(HTML) 61 Page - Infineon Technologies AG |
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61 / 93 page ![]() Data Sheet 61 Rev. 1.0, 2009-03-31 TLE8262E Interrupt Function 12.1.1 Interrupt for switching on Vcc2 and Vcc3 The Interrupt for Vcc2 and Vcc3 are generated when the SPI command for switching on the voltage regulator is executed. The interrupt bit is set to “1“ and can be cleared with a Read Only command after the under voltage threshold is reached. If the Read Only is done before the reset threshold is reached, the interrupt bit can not be cleared as the undervoltage condition is still present. In this case a second interrupt can be issued for releasing the undervoltage condition. In case of a short to GND on Vcc2 or Vcc3 the interrupt for switching on the voltage regulator is issued, but the µC can not clear the interrupt bit as the voltage regulator does not reach the undervoltage threshold. 12.1.2 Example of Interrupt Events and Read-out The examples show single interrupt events. SPI read is done with “Read Only”. The shown interrupts are not masked. Watchdog trigger is not shown in the examples. The interrupt UV_Vcc2 that is generated by switching on V CC2 is shown in Figure 27. The interrupt is sensitive on rising event only. Undervoltage at V CC2 (except during switch off 1)) Rising and falling UV _VCC2 Event / State Undervoltage at V CC3(except during switch off 1)) Rising and falling UV _VCC3 Over current at V CC3 (except during inhibition) Rising I CC3 > ICC3MAX Voltage at V CC2 (during switch on 1)) Rising UV _VCC2 Event Voltage at V CC3 (during switch on 1)) Rising UV _VCC3 SBC Failure SPI data corrupted Rising SPI Fail Event Reset (SBC SW Development only) Rising Reset Wrong watchdog setting Rising Wrong WD set Wake Wake at CAN Rising WK CAN Event Wake at LIN Rising WK LINx Wake at WK Rising WK WK pin 1..0 Cyclic WK Rising Cyclic WK 1) When VCC2/3 is switched off no interrupt is generated due to the undervoltage at VCC2/3. When switching on VCC2/3 an interrupt is generated when the command is sent to the SBC via SPI. Table 11 Interrupt sources Interrupt sources INT Activation SPI bit State |
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