ATtiny25-15ST datasheet(72/196 Pages) ATMEL

72 / 196 page

7598H–AVR–07/09

ATtiny25/45/85

Figure 12-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-

caler (f

clk_I/O/8)

12.8

8-bit Timer/Counter Register Description

12.8.1

Timer/Counter Control Register A – TCCR0A

• Bits 7:6 – COM01A:0: Compare Match Output A Mode

These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0

bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin

must be set in order to enable the output driver.

When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the

WGM02:0 bit setting. Table 12-1 shows the COM0A1:0 bit functionality when the WGM02:0 bits

are set to a normal or CTC mode (non-PWM).

Table 12-2 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM

mode.

OCFnx

OCRnx

TCNTn

(CTC)

TOP

TOP - 1

TOP

BOTTOM

BOTTOM + 1

clk

I/O

clk

(clk

I/O/8)

Bit

210

COM0A1

COM0A0

COM0B1

COM0B0

–

WGM01

WGM00

TCCR0A

Read/Write

R/W

Initial Value

Table 12-1.

Compare Output Mode, non-PWM Mode

COM01

COM00

Description

Normal port operation, OC0A disconnected.

Toggle OC0A on Compare Match

Clear OC0A on Compare Match

Set OC0A on Compare Match

Table 12-2.

Compare Output Mode, Fast PWM Mode

(1)

COM01

COM00

Description

Normal port operation, OC0A disconnected.

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