ATtiny25-15ST datasheet(86/196 Pages) ATMEL

86 / 196 page

7598H–AVR–07/09

ATtiny25/45/85

• Bit 3- FOC1B: Force Output Compare Match 1B

Writing a logical one to this bit forces a change in the compare match output pin PB3 (OC1B)

according to the values already set in COM1B1 and COM1B0. If COM1B1 and COM1B0 written

in the same cycle as FOC1B, the new settings will be used. The Force Output Compare bit can

be used to change the output pin value regardless of the timer value. The automatic action pro-

grammed in COM1B1 and COM1B0 takes place as if a compare match had occurred, but no

interrupt is generated. The FOC1B bit always reads as zero. FOC1B is not in use if PWM1B bit

is set.

• Bit 2- FOC1A: Force Output Compare Match 1A

Writing a logical one to this bit forces a change in the compare match output pin PB1 (OC1A)

according to the values already set in COM1A1 and COM1A0. If COM1A1 and COM1A0 written

in the same cycle as FOC1A, the new settings will be used. The Force Output Compare bit can

be used to change the output pin value regardless of the timer value. The automatic action pro-

grammed in COM1A1 and COM1A0 takes place as if a compare match had occurred, but no

interrupt is generated. The FOC1A bit always reads as zero. FOC1A is not in use if PWM1A bit

is set.

• Bit 1- PSR1 : Prescaler Reset Timer/Counter1

When this bit is set (one), the Timer/Counter prescaler (TCNT1 is unaffected) will be reset. The

bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have

no effect. This bit will always read as zero.

14.1.3

Timer/Counter1 - TCNT1

This 8-bit register contains the value of Timer/Counter1.

Timer/Counter1 is realized as an up counter with read and write access. Due to synchronization

of the CPU, Timer/Counter1 data written into Timer/Counter1 is delayed by one and half CPU

clock cycles in synchronous mode and at most one CPU clock cycles for asynchronous mode.

14.1.4

Timer/Counter1 Output Compare RegisterA - OCR1A

The output compare register A is an 8-bit read/write register.

The Timer/Counter Output Compare Register A contains data to be continuously compared with

Timer/Counter1. Actions on compare matches are specified in TCCR1. A compare match does

only occur if Timer/Counter1 counts to the OCR1A value. A software write that sets TCNT1 and

OCR1A to the same value does not generate a compare match.

A compare match will set the compare interrupt flag OCF1A after a synchronization delay follow-

ing the compare event.

Bit

765

43210

$2F ($4F)

MSB

LSB

TCNT1

Read/Write

R/W

Initial value

000

00000

Bit

765

43210

$2E ($4E)

MSB

LSB

OCR1A

Read/Write

R/W

Initial value

000

00000

ATtiny25-15ST Datenblatt(PDF) 86 Page - ATMEL Corporation

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