ATmega32A datasheet(34/352 Pages) ATMEL

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8155B–AVR–07/09

ATmega32A

face, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep

mode basically halts clk

CPU and clkFLASH, while allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal

ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the

Analog Comparator interrupt is not required, the Analog Comparator can be powered down by

setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will

reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati-

cally when this mode is entered.

9.3

ADC Noise Reduction Mode

When the SM2:0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC

Noise Reduction mode, stopping the CPU but allowing the ADC, the External Interrupts, the

Two-wire Serial Interface address watch, Timer/Counter2 and the Watchdog to continue operat-

ing (if enabled). This sleep mode basically halts clk

I/O, clkCPU, and clkFLASH, while allowing the

other clocks to run.

This improves the noise environment for the ADC, enabling higher resolution measurements. If

the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the

ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out

Reset, a Two-wire Serial Interface Address Match Interrupt, a Timer/Counter2 interrupt, an

SPM/EEPROM ready interrupt, an External level interrupt on INT0 or INT1, or an external inter-

rupt on INT2 can wake up the MCU from ADC Noise Reduction mode.

9.4

Power-down Mode

When the SM2:0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-

down mode. In this mode, the External Oscillator is stopped, while the External interrupts, the

Two-wire Serial Interface address watch, and the Watchdog continue operating (if enabled).

Only an External Reset, a Watchdog Reset, a Brown-out Reset, a Two-wire Serial Interface

address match interrupt, an External level interrupt on INT0 or INT1, or an External interrupt on

INT2 can wake up the MCU. This sleep mode basically halts all generated clocks, allowing oper-

ation of asynchronous modules only.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed

level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 69

for details.

When waking up from Power-down mode, there is a delay from the wake-up condition occurs

until the wake-up becomes effective. This allows the clock to restart and become stable after

having been stopped. The wake-up period is defined by the same CKSEL fuses that define the

reset time-out period, as described in “Clock Sources” on page 26.

9.5

Power-save Mode

When the SM2:0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-

save mode. This mode is identical to Power-down, with one exception:

If Timer/Counter2 is clocked asynchronously, i.e., the AS2 bit in ASSR is set, Timer/Counter2

will run during sleep. The device can wake up from either Timer Overflow or Output Compare

event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in

TIMSK, and the Global Interrupt Enable bit in SREG is set.

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