ATmega32A datasheet(39/352 Pages) ATMEL

39 / 352 page

8155B–AVR–07/09

ATmega32A

Figure 10-1. Reset Logic

10.2.1

Power-on Reset

A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level

is defined in “System and Reset Characteristics” on page 299. The POR is activated whenever

CC is below the detection level. The POR circuit can be used to trigger the Start-up Reset, as

well as to detect a failure in supply voltage.

A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the

Power-on Reset threshold voltage invokes the delay counter, which determines how long the

device is kept in RESET after V

CC rise. The RESET signal is activated again, without any delay,

when V

CC decreases below the detection level.

Figure 10-2. MCU Start-up, RESET Tied to V

CC.

MCU Control and Status

BODEN

BODLEVEL

Delay Counters

CKSEL[3:0]

TIMEOUT

DATA BUS

Clock

Generator

SPIKE

FILTER

Pull-up Resistor

JTAG Reset

Watchdog

Oscillator

SUT[1:0]

Watchdog

Timer

Reset Circuit

Brown-out

Reset Circuit

Power-on

Reset Circuit

RESET

TIME-OUT

INTERNAL

RESET

TOUT

POT

RST

ATmega32A Datenblatt(PDF) 39 Page - ATMEL Corporation

ATmega32A Datenblatt(HTML) 39 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL