MPC8536BVTATH datasheet(122/128 Pages) FREESCALE

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MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2

Guidelines for High-Speed Interface Termination

Freescale Semiconductor

122

The following pins must be connected to XGND if not used:

•

SD1_RX[7:0]

•

SD1_RX[7:0]

•

SD1_REF_CLK

•

SD1_REF_CLK

3.11.3

SerDes 2 Interface Entirely Unused

If the high-speed SerDes 2 interface (SGMII/ SATA) is not used at all, the unused pin should be terminated as described in this

section. See SerDes2 in Table 1 for details.

The following pins must be left unconnected (float):

•

SD2_TX[1:0]

•

SD2_TX[1:0]

•

Reserved pins L8, L9

The following pins must be connected to X2GND:

•

SD2_RX[1:0]

•

SD2_RX[1:0]

•

SD2_REF_CLK

•

SD2_REF_CLK

The POR configuration pin cfg_srds2_prtcl[0:2] on TSEC1_TXD[2], TSEC3_TXD[2], TSEC_1588_PUSLE_OUT1 can be

used to power down SerDes 2 block for power saving. Note that both S2VDD and X2VDD must remain powered.

3.11.4

SerDes 2 Interface Partly Unused

If only part of the high speed SerDes 2 (SGMII/SATA) interface pins are used, the remaining high-speed serial I/O pins should

be terminated as described in this section.

The following pins must be left unconnected (float) if not used:

•

SD2_TX[1:0]

•

SD2_TX[1:0]

•

Reserved pins: T22, T23

The following pins must be connected to X2GND if not used:

•

SD2_RX[1:0]

•

SD2_RX[1:0]

Ordering Information

Ordering information for the parts fully covered by this specification document is provided in Section 4.1, “Part Numbers Fully

Addressed by This Document.”

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