MPC8536BVTATH datasheet(118/128 Pages) FREESCALE

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MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2

Configuration Pin Muxing

Freescale Semiconductor

118

3.9

Configuration Pin Muxing

The MPC8536E provides the user with power-on configuration options which can be set through the use of external pull-up or

pull-down resistors of 4.7 k

Ω on certain output pins (see customer visible configuration pins). These pins are generally used as

output only pins in normal operation.

While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins while HRESET is

asserted, is latched when HRESET deasserts, at which time the input receiver is disabled and the I/O circuit takes on its normal

function. Most of these sampled configuration pins are equipped with an on-chip gated resistor of approximately 20 k

Ω. This

value should permit the 4.7-k

Ω resistor to pull the configuration pin to a valid logic low level. The pull-up resistor is enabled

only during HRESET (and for platform /system clocks after HRESET deassertion to ensure capture of the reset value). When

the input receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with minimal signal

quality or delay disruption. The default value for all configuration bits treated this way has been encoded such that a high voltage

level puts the device into the default state and external resistors are needed only when non-default settings are required by the

user.

Careful board layout with stubless connections to these pull-down resistors coupled with the large value of the pull-down

resistor should minimize the disruption of signal quality or speed for output pins thus configured.

The platform PLL ratio and e500 PLL ratio configuration pins are not equipped with these default pull-up devices.

3.10

JTAG Configuration Signals

Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 78.

Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most

have asynchronous behavior and spurious assertion will give unpredicatable results.

Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1

specification, but it is provided on all processors built on Power Architecture technology. The device requires TRST to be

asserted during power-on reset flow to ensure that the JTAG boundary logic does not interfere with normal chip operation.

While the TAP controller can be forced to the reset state using only the TCK and TMS signals, generally systems assert TRST

during the power-on reset flow. Simply tying TRST to HRESET is not practical because the JTAG interface is also used for

accessing the common on-chip processor (COP), which implements the debug interface to the chip.

The COP function of these processors allow a remote computer system (typically, a PC with dedicated hardware and debugging

software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG

port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert

HRESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage

monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into

these signals with logic.

The arrangement shown in Figure 78 allows the COP port to independently assert HRESET or TRST, while ensuring that the

target can drive HRESET as well.

Table 81. Impedance Characteristics

Impedance

Local Bus, Ethernet, DUART,

Control, Configuration, Power

Management

PCI

DDR DRAM

Symbol Unit

45 Target

45 Target (cfg_pci_impd=1)

25 Target (cfg_pci_impd=0)

18 Target (full strength mode)

36 Target (full strength mode)

45 Target

45 Target (cfg_pci_impd=1)

25 Target (cfg_pci_impd=0)

18 Target (full strength mode)

36 Target (full strength mode)

Note: Nominal supply voltages. See Table 1.

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