ADS58C48IPFPR datasheet(22/70 Pages) TI

22 / 70 page

ADS58C48

SLAS689 – MAY 2010

www.ti.com

ADDRS

DEFAULT

A7-A0 IN

VALUE

HEX

AFTER

RESET

<CMOS CLKOUT

STRENGTH>

D7-D6

LVDS interface

CMOS interface

D5-D4

Maximum strength (recommended and used for specified timings)

Medium strength

Low strength

Very low strength

D1-D0

LVDS data buffers enabled for all channels

LVDS data buffers powered down and output 3-stated for channel A and channel D

LVDS data buffers powered down and output 3-stated for channel B and channel C

LVDS data buffers powered down and output 3-stated for all channels including the LVDS output

clock buffer

ADDRS

DEFAULT

A7-A0 IN

VALUE

HEX

AFTER

RESET

<CLKOUT RISE

<DIGITAL

POSN>

MODE 1>

D7-D6

Default position (timings are specified in this condition)

Setup increases by 450 ps, hold decreases by 450 ps

Setup decreases by 300 ps, Hold increases by 300 ps

In this setting, the bit order is swapped compared to default case.

For example, default order is [CLKOUTP fall-D1, CLKOUTP rise –D2]. In this setting, the order

becomes [CLKOUTP fall-D2, CLKOUTP rise –D1]

Setup increases by 1.0 ns, Hold decreases by 1.0 ns

D5-D4

Default position (timings are specified in this condition)

Setup increases by 550 ps, hold decreases by 550 ps

Setup increases by 600 ps, Hold decreases by 600 ps

In this setting, the bit order is swapped compared to default case.

For example, default order is [CLKOUTP fall-D1, CLKOUTP rise –D2] In this setting, the order

becomes [CLKOUTP fall-D2, CLKOUTP rise –D1]

Setup increases by 1.1 ns, Hold decreases by 1.1 ns

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