MSC8252 datasheet(32/68 Pages) FREESCALE

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MSC8252 Dual-Core Digital Signal Processor Data Sheet, Rev. 3

Electrical Characteristics

Freescale Semiconductor

Note:

Specifications are valid at the recommended operating conditions listed in Table 3.

2.5.3.3

DC-Level Requirements for Serial RapidIO Configurations

This sections provided various DC-level requirements for Serial RapidIO Configurations.

Note:

Specifications are valid at the recommended operating conditions listed in Table 3.

Table 11. PCI Express (2.5 Gbps) Differential Transmitter (Tx) Output DC Specifications

Parameter

Symbol

Min

Typical

Max

Units

Notes

Differential peak-to-peak output voltage

VTX-DIFFp-p

800

1000

1200

De-emphasized differential output voltage (ratio)

VTX-DE-RATIO

3.0

3.5

4.0

DC differential Tx impedance

ZTX-DIFF-DC

100

120

Transmitter DC impedance

ZTX-DC

Notes:

VTX-DIFFp-p = 2 × |VTX-D+ – VTX-D-| Measured at the package pins with a test load of 50 Ω to GND on each pin.

Ratio of the VTX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of the first bit after a

transition. Measured at the package pins with a test load of 50

Ω to GND on each pin.

Tx DC differential mode low impedance

Required Tx D+ as well as D– DC Impedance during all states

Table 12. PCI Express (2.5 Gbps) Differential Receiver (Rx) Input DC Specifications

Parameter

Symbol

Min

Typical

Max

Units

Notes

Differential input peak-to-peak voltage

VRX-DIFFp-p

120

1000

1200

DC differential Input Impedance

ZRX-DIFF-DC

100

120

DC input impedance

ZRX-DC

Powered down DC input impedance

ZRX-HIGH-IMP-DC

—

ΚΩ

Electrical idle detect threshold

VRX-IDLE-DET-DIFFp-p

—

175

Notes:

VRX-DIFFp-p = 2 × |VRX-D+ – VRX-D-| Measured at the package pins with a test load of 50 Ω to GND on each pin.

Rx DC differential mode impedance. Impedance during all LTSSM states. When transitioning from a fundamental reset to

detect (the initial state of the LTSSM), there is a 5 ms transition time before the receiver termination values must be met on all

unconfigured lanes of a port.

Required Rx D+ as well as D– DC Impedance (50 ±20% tolerance). Measured at the package pins with a test load of 50

Ω to

GND on each pin. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state

of the LTSSM), there is a 5 ms transition time before the receiver termination values must be met on all unconfigured lanes of

a port.

Required Rx D+ as well as D– DC Impedance when the receiver terminations do not have power. The Rx DC common mode

impedance that exists when no power is present or fundamental reset is asserted. This helps ensure that the receiver detect

circuit does not falsely assume a receiver is powered on when it is not. This term must be measured at 300 mV above the Rx

ground.

VRX-IDLE-DET-DIFFp-p = 2 × |VRX-D+ –VRX-D–|. Measured at the package pins of the receiver

Table 13. Serial RapidIO Transmitter DC Specifications

Parameter

Symbol

Min

Typical

Max

Units

Notes

Output voltage

–0.40

—

2.30

Long run differential output voltage

VDIFFPP

800

—

1600

mVp-p

—

Short run differential output voltage

VDIFFPP

500

—

1000

mVp-p

—

Note:

Voltage relative to COMMON of either signal comprising a differential pair.

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