MSC8252 datasheet(58/68 Pages) FREESCALE

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MSC8252 Dual-Core Digital Signal Processor Data Sheet, Rev. 3

Hardware Design Considerations

Freescale Semiconductor

3.5.1

DDR Memory Related Pins

This section discusses the various scenarios that can be used with either of the MSC8252 DDR ports.

Note:

The signal names in Table 40, Table 41 and Table 42 are generic names for a DDR SDRAM interface. For actual pin

names refer to Table 1.

3.5.1.1

DDR Interface Is Not Used

Table 40. Connectivity of DDR Related Pins When the DDR Interface Is Not Used

Signal Name

Pin Connection

MDQ[0–63]

MDQS[7–0]

MA[15–0]

MCK[0–2]

MCS[1–0]

MDM[7–0]

MBA[2–0]

MCAS

MCKE[1–0]

MODT[1–0]

MMDIC[1–0]

MRAS

MWE

MECC[7–0]

MDM8

MDQS8

MAPAR_OUT

MAPAR_IN

MVREF3

GVDD1/GVDD23

Notes:

For the signals listed in this table, the initial M stands for M1 or M2 depending on which DDR controller is not used.

If the DDR controller is not used, disable the internal DDR clock by setting the appropriate bit in the System Clock Control

Clocks and General Configuration Registers chapters in the MSC8252 Reference Manual for details.

For MSC8252 Revision 1 silicon, these pins were connected to GND. For newer revisions of the MSC8252, connecting these

pins to GND increases device power consumption.

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