MSC8252 datasheet(37/68 Pages) FREESCALE

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Electrical Characteristics

MSC8252 Dual-Core Digital Signal Processor Data Sheet, Rev. 3

Freescale Semiconductor

Figure 11 shows the DDR2 and DDR3 SDRAM interface input timing diagram.

2.6.1.2

DDR SDRAM Output AC Timing Specifications

Table 21 provides the output AC timing specifications for the DDR SDRAM interface.

Figure 11. DDR2 and DDR3 SDRAM Interface Input Timing Diagram

Table 21. DDR SDRAM Output AC Timing Specifications

Parameter

Symbol 1

Min

Max

Unit

Notes

MCK[n] cycle time

tMCK

2.5

ADDR/CMD output setup with respect to MCK

• 800 MHz data rate

• 667 MHz data rate

tDDKHAS

0.917

1.10

—

ADDR/CMD output hold with respect to MCK

• 800 MHz data rate

• 667 MHz data rate

tDDKHAX

0.767

1.02

—

MCSn output setup with respect to MCK

• 800 MHz data rate

• 667 MHz data rate

tDDKHCS

0.917

1.10

—

MCSn output hold with respect to MCK

• 800 MHz data rate

• 667 MHz data rate

tDDKHCX

0.767

1.02

—

MCK to MDQS Skew

• 800 MHz data rate

• 667 MHz data rate

tDDKHMH

–0.4

–0.6

0.375

0.6

MDQ/MECC/MDM output setup with respect to MDQS

• 800 MHz

• 667 MHz

tDDKHDS,

tDDKLDS

300

375

—

MDQ/MECC/MDM output hold with respect to MDQS

• 800 MHz

• 667 MHz

tDDKHDX,

tDDKLDX

300

375

—

MDQS preamble

tDDKHMP

–0.9

× tMCK

—ns

—

MDQS postamble

tDDKHME

–0.4

× tMCK

–0.6

× tMCK

—

MCK[n]

tMCK

MDQ[n]

MDQS[n]

tDISKEW

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