LM27402 datasheet(21/32 Pages) NSC

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CND_LS is the conduction loss of the low-side FET during the

1-D cycle when current is flowing through the on-resistance

of the FET. R

DS(ON)_LS (Ω) is the drain to source resistance.

D is the deadtime power loss due to the body diode drop of

the low-side FET. T

deadtime (s) is the total deadtime.

RR is the reverse recovery charge power loss. QRR (C) is the

total reverse recovery charge usually specified in the FET

datasheet. P

TOT_LS is the total power dissipation of the low-

side FET.

Gate Charge Loss

A finite amount of gate charge is required in order to switch

the high-side and low-side FETs. This gate charge is contin-

uously charging the FETs during every switching cycle and

appears as a constant current flowing into the controller from

the input supply. The next equation describes the power loss

due to the gate charge.

QG is the total gate charge power loss, QGHS (C) and QGLS

tively, and can be found in the FET datasheets,V

IN (V) is the

input voltage, and f

SW (Hz) is the switching frequency.

Input and Output Capacitor ESR Losses

Both the input and output capacitors are subject to steady

state AC current and must be taken into consideration when

calculating power losses. The next equation shown is the in-

put capacitor ESR power loss.

The input capacitor power loss equation includes the effective

series resistance or R

ESR_IN (Ω) of the input capacitor. The

power loss due to the ESR of the output capacitor is:

The output capacitor power loss equation includes the peak

to peak inductor current,

ΔI

L(A), and the effective series re-

sistance or R

ESR (Ω) of the output capacitor.

Inductor Losses

The losses due to the inductor are caused primarily by the

DCR. The next equation calculates the inductor DCR power

loss.

DCR is the total power loss of the Inductor. A self heating

coefficient of 1.2 is included in this equation to approximate

the effects of the copper temperature coefficient approxi-

mately equal to 3900ppm/°C. R

DCR (Ω) is the inductor DC

resistance.

Controller Losses

The controller loss remains constant and contributes to a very

small loss of power. The quiescent current is the main factor

in terms of power loss attributed to the controller and it re-

mains constant at 4 mA. The quiescent current power loss

equation is:

The controller I

Q power loss equation includes the IQ current

(4 mA) and input voltage V

IN (V).

It is also important to calculate the power dissipated in the

controller itself due to the gate charge current flowing from

VIN to the output of the LDO (VDD). The gate charge current

essentially passes through a resistance dropping the input

voltage VIN to the LDO voltage (4.5V). This can cause the

controller to operate at an elevated temperature since it must

dissipate the power of the LDO pass device. The next equa-

tion calculates the power dissipated by the internal LDO of the

controller.

LDO is the power dissipated in the LDO, QGHS (C) and

GLS are the high-side and low-side FET gate charges, re-

spectively, and can be found in the FET datasheets.

Overall Efficiency

After calculating the losses, the efficiency can then be calcu-

lated using:

PCB LAYOUT CONSIDERATIONS

After selecting the correct components, PCB layout is another

crucial step in optimizing a buck regulator. The layout must

be able to handle large DC and AC currents, minimize switch-

node noise, and spread heat. The following layout guidelines

and tips will help increase the chances of a successful design

and should be taken seriously during the layout process.

Input and Output Capacitor Layout

A buck regulator is a switching converter with switched cur-

rents and voltages. The high di/dt and dv/dt nature of buck

switching calls for careful layout of decoupling capacitors. The

next figures shows the switching currents for the D and 1-D

intervals of a buck regulator.

30092665

FIGURE 19. Power Flow

During the high-side FET on time, the AC component of the

input current is supplied by the input capacitor. Due to the high

di/dt nature of this current, it is essential that the input capac-

itor is closely coupled to the drain of the high-side FET to

minimize any parasitic inductance. The output capacitor re-

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